The meeting must have been good, as there was no more pizza left. While there's enthusiasm and energy to spare, the next one will be on Friday, 2/22, 11:30-1. The agenda:

1. 15-20 min. of brainstorming process issues (Maryam has a process issue to present) and follow up on action items from previous Grand Rounds.

2. Proposals for Superuser/Quality Circle programs.

Here's a summary of the last meeting:

Topic #1: Review of ASML handling.

Binder presented an slides and a video showing the ASML transport mechanism. It appears that the wafer must make vacuum on:

A. three different vacuum wands (the robot arm and two arms of the dipod) with small "pocket" areas which make vacuum contact at some point nearer an edge of the wafer

B. The prealigner chuck, which has two small pockets for making vacuum contact near the middle of the wafer

C. The "E" chuck, which has a vacuum ring, near the perimeter of the wafer.

No wonder curved wafers get stuck! Gary Sosa is partly trained on retrieving stuck wafers, but those stuck on the "E" chuck require ASML intervention for now. To avoid having the system go down for a stuck wafer overnight or a long weekend, we need to ensure people check their wafers before loading. If in doubt, please save wafers for regular working hours.

Action Items:

- ASML/Mahnaz/ASML Users: Post procedure and sample wafers for the "granite stone" test. This is a gross check for wafer flatness. A wafer with any significant curvature won't "float" on the ultraflat granite table. (Done - Mahnaz, Binder, and Linda.) Wafers should be checked before using the ASML on off-hours, to avoid having the system go down off-shift. Wafers that fail should be processed only with ASML present, for now.

- ASML/SNF: ASML to provide specs on wafer curvature and handling. SNF to post on local server for users.

- ASML/Mahnaz/Epi users: Test curved-wafer to handle-wafer method. Handle-wafer has a trimmed flat, so flat finding can be (theoretically) done on the curved-wafer. ASML recommends that some adjustments to the leveling algorithm should also be done. It is generally thought this method could be used to get curved wafers loaded, but that critical resolution is not likely to be achieved.

- ASML/Gary S: Partly done. Gary can retrieve wafers short of the e-chuck.

- ASML/SNF: Build an alignment jig for device-wafer to handling-wafer mounting. (This arose when ASML was trying to help a user whose wafer broke into two.)

- SNF: Paul R. offers to support anyone wishing to characterize their wafers on the FSM stress gage. Call is in for repair of the Tencor stress gage.

Topic #2: STS Etch Brainstorming

There was some discussion about the intermittent "plasma-off" problem observed on stsetch1. I believe the consensus was that this could pose a serious problem for people doing critical etches, but probably not for those "drilling holes." There has also been a significant drop in etch rates some time early to mid last year, from about 3.2 um/min for "deep" to about 2.6 um/min.

Following on this, there was much discussion of the status and use of stsetch2, namely:

A. How to do through-wafer etching.

- Use of a holder: There are concerns about materials to use, since plasma density is so much higher on stsetch2 than on #1. Holder material is expected to sputter off, leading to possible cross-contamination concerns and redeposition leading to "grassing" on wafers, especially around edges.

- Use of bonded wafers. Resist has been explored, although burning has been observed. Berkeley uses "cool grease". Effectiveness appears highly dependent on technique.

B. Plans for designating one tool as "gold-contaminated." Since stsetch1 and stsetch2 are not interchangeable, it has been diffficult to execute on this. Outstanding issues:

- How to do through wafer etching, per above.

- stsetch2 exhibits undercutting/CD loss not observed on stsetch1.

- SOI etching on stsetch2 is not well understood.

- Resist burning and substrate temperature during processing in stsetch2 are not understood. (And how would this affect through-wafer etching?)

- stsetch2 is a special "HRM" system. It appears STS didn't sell many of these and does not have extensive process expertise to offer.

C. What does the stsetch/2 user community want?

Action items:

- SNF: Find a way to monitor the plasma-off problem on stsetch1.

- stsetch users: Report plasma-off (and other) observations on Coral.

- Ed/Nahid: Assemble and share data from last year's REU/RET program.

- Ed/SNF: Jim McVittie did some contamination characterization experiments on stsetch1 some years ago. We need to obtain and examine these results.

- Ed: Present stsetch2 RSM characterization results (at a future Grand Rounds?)

- Ed/J: Acquire and test cool grease (from Berkeley -- or find where to get it and order ourselves.)

- Ed/Mary: Contact other STS etch owners (at NNIN sites and elsewhere) and find out what they do for through wafer etching.

- SpecMat:Work to resolve Nahid's request.

- All: Assemble available etch rate data. (Nancy has zygo etch rates going back to last summer and limited data from before then. If anyone has definitive data from before then, please contact Nancy.)

- Nahid, Mario, Joey, w/input from SNF Staff: Develop an STS etch users survey to gage the user community's needs for DRIE. Survey should include questions about: substrate size requirements; substrates (SOI or not?); etch depth; minimum CD feature requirements (whether CD loss will be acceptable); contamination requirements/acceptable contamination levels; etc.